Fabrication of stacked die and structures formed thereby

ABSTRACT

Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device side of a second die, wherein forming the bond between the non-device side of the first die and the non-device side of the second die does not comprise using an interfacial glue.

FIELD OF THE INVENTION

The present invention generally relates to the field of microelectronicdevices, and more particularly to methods of fabricating stacked diestructures without the use of an interfacial glue.

BACKGROUND OF THE INVENTION

Integrated circuits form the basis for many electronic systems. Anintegrated circuit may include a vast number of transistors and othercircuit elements that may be formed on a single semiconductor wafer orchip and may be interconnected to implement a desired function.

Many modern electronic systems are created through the use of a varietyof different integrated circuits; each integrated circuit performing oneor more specific function. For example, computer systems may include atleast one microprocessor and a number of memory chips. Conventionally,each of these integrated circuits are formed on a separate chip,packaged independently and interconnected on, for example, a printedcircuit board (PCB).

As integrated circuit technology progresses, there is a growing desirefor a “system on a chip”, in which the functionality of all of theintegrated circuit devices of the system are packaged together without aconventional PCB. In practice, various “system modules” have beenintroduced that electrically connect and package integrated circuitdevices which are fabricated on the same or on different semiconductorwafers. Initially, system modules have been created by simply stackingtwo chips, e.g., a logic and memory chip, one on top of the other in anarrangement commonly referred to as chip-on-chip structure.Subsequently, multi-chip module (MCM) technology has been utilized tostack a number of chips on a common substrate to reduce the overall sizeand weight of the package, which directly translates into reduced systemsize.

BRIEF DESCRIPTION OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming certain embodiments of the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIGS. 1a-1e represent structures according to an embodiment of thepresent invention.

FIG. 2 represents a structure according to an embodiment of the presentinvention.

FIG. 3 represents a structure according to another embodiment of thepresent invention.

FIG. 4 represents a system according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that the variousembodiments of the invention, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein, in connection with one embodiment, maybe implemented within other embodiments without departing from thespirit and scope of the invention. In addition, it is to be understoodthat the location or arrangement of individual elements within eachdisclosed embodiment may be modified without departing from the spiritand scope of the invention. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims, appropriatelyinterpreted, along with the full range of equivalents to which theclaims are entitled. In the drawings, like numerals refer to the same orsimilar functionality throughout the several views.

Methods and associated structures of forming and utilizing amicroelectronic device are described. Those methods comprise forming abond between a non-device side of a first die and a non-device side of asecond die, without the use of an interfacial glue. In this manner,improved thermal and electrical contact, as well as a decrease in stressbetween the bonded die, can be achieved.

FIGS. 1a-1e illustrate an embodiment of a method of forming stacked diestructures. FIG. 1a illustrates a device wafer 100. The device wafer 100may be comprised of materials such as, but not limited to, silicon,silicon-on-insulator, silicon on diamond, or combinations thereof. Thedevice wafer 100 may comprise a device portion 103, and a non-deviceportion 104. The non-device portion 104 of the device wafer 100 maycomprise a first thickness 106. The device wafer 100 may comprise aplurality of die 101, as are known in the art. The plurality of die 101may comprise various functionalities, such as, but not limited to, amemory functionality and/or a logic functionality, as are well known inthe art.

The non-device portion 104 of the device wafer 100 may be thinnedutilizing a grinding and/or a polishing technique, as are known in theart (FIG. 1b ). The non-device portion 104 of the device wafer 100 maybe thinned to a thinned thickness 108. In one embodiment, the thinnedthickness 108 may range from about 50 to about 200 microns. The devicewafer 100 may then be separated into a plurality of individual die 102utilizing methods well known to those skilled in the art, such as butnot limited to wafer sawing, which serve to separate the plurality ofdie 101 from each other (FIG. 1c ).

The plurality of individual die 102 may comprise a device side 110 and anon-device side 112. In one embodiment, the non-device side 112 maycomprise silicon. The device side 110 may comprise various circuitelements, such as but not limited to transistors, resistors etc. as arewell known in the art. In one embodiment, a first individual die 102 amay comprise a device side 110 a and a non-device side 112 a (FIG. 1d ).A second individual die 102 b may comprise a device side 110 b and anon-device side 112 b. The non-device side 112 a of the first individualdie 102 a may be brought into contact with the non-device side 112 b ofthe second individual die 102 b to form a stacked die structure 116(FIG. 1e ).

Upon contacting the non-device side 112 a of the first individual die102 a with the non-device side 112 b of the second individual die 102 b,a bond 114 may be formed by direct silicon to silicon bonding betweenthe non-device side 112 a of the first individual die 102 a and thenon-device side 112 b of the second individual die 102 b. The bond 114may be formed due to Van der Waal forces that may develop between thenon-device side 112 a (which may comprises silicon) of the firstindividual die 120 a and the non-device side 112 b (which alsopreferably comprises silicon) of the second individual die 102 b. In oneembodiment, the bond 114 can be further strengthened by heating thestacked die structure 116 to a temperature up to about 450 degreesCelsius, and in another embodiment, by heating from about 250 degrees toabout 450 degrees Celsius.

Forming the bond 114 by utilizing direct silicon to silicon bondingaccording to the methods of the present embodiment alleviates the needfor using an interfacial glue, i.e., polymers, adhesives, solders, andother such materials commonly used to join one die to another, as arewell known in the art. The elimination of such an interfacial glue, orjoining material, to form the bond 114 between the first individual die102 a and the second individual die 102 b results in better thermal andelectrical contact between the die, due to the low coefficient ofthermal expansion (CTE) differences between the die. The CTE differencesbetween the die may be approximately zero when both of the die comprisesilicon, for example.

Thus, deleterious thermal barriers may be eliminated between the diejoined according to the methods of the present embodiment. In addition,stress between die joined according to the present embodiment aregreatly reduced, if not eliminated due to the matching of the CTE'sbetween the joined die. Yet another advantage of joining the die withoutthe use of interfacial glue is that the directly bonded die reinforceeach other by increasing rigidity and reducing the strain that wouldtypically be introduced by joining the die with an interfacial glue.Increasing rigidity and reducing strain decreases undesirable shifts inelectrical parameters. Yet another advantage of the present embodimentis that the mechanical strength of the bond 114 is improved by utilizingdirect silicon to silicon bonding, and in one embodiment the mechanicalstrength of the bond may comprise at least about 1500 KPa.

FIG. 2 depicts an embodiment of a stacked die structure 216 that maycomprise a first individual die 202 a, a second individual die 202 b, athird individual die 202 c, and a fourth individual die 202 d. In oneembodiment, the individual die 202 a, 202 b, 202 c, 202 d may comprisevarious functionalities, such as but not limited to memoryfunctionalities and/or logic functionalities. The individual die 202 a,202 b, 202 c, 202 d may comprise device sides 210 a, 210 b, 210 c, 210 dand non-device sides 212 a, 212 b, 212 c, 212 d, respectively. In oneembodiment, the non-device sides 212 a, 212 b, 212 c, 212 d maypreferably comprise silicon.

The non-device side 212 a of the first individual die 202 a may bebonded to the non-device side 212 b of the second individual die 202 b(by direct silicon to silicon bonding, as described above) to form abond 214 a, similar to the bond 114 in FIG. 1e . The bond 214 a does notcomprise an interfacial glue. In like manner, the non-device side 212 cof the third individual die 202 c may be bonded to the non-device side212 d of the fourth individual die 202 d to form a bond 214 b, that issimilar to the bond 114 of FIG. 1e , and which does not comprise aninterfacial glue.

The device side 210 a of the first individual die 202 a may comprise afirst array of contacts 206 a, such as but not limited to ball gridarray contacts, for example. Similarly, the device side 210 b of thesecond individual die 202 b may comprise an second array of contacts 206b. The first array of contacts 206 a may be electrically contactedand/or attached to a bottom surface 215 a of a first land grid array 208a, as is well known in the art. The first land grid array may alsocomprise a top surface 213 a. The second array of contacts 206 b may beelectrically connected and/or attached to a top surface 213 b of asecond land grid array 208 b.

The first land grid arrays 208 a and the second land grid array 208 bmay comprise a first organic land grid array and a second organic landgrid array, but may comprise any such suitable substrate that may beelectrically and/or physically connected to a semiconductor die. It willbe understood by those in the art that the land grid arrays 208 a, 208 bmay comprise an array of contacts (not shown) on both their top sides213 a, 213 b, and their bottom sides 215 a, 215 b that correspond andare in electrical and/or physical connection with the array of contacts206 a, 206 b. Thus, the non-device sides 212 a, 212 b of the first andthe second individual die 202 a,202 b may be bonded together by directsilicon to silicon bonding, and the device sides 210 a, 210 b of thefirst and second individual die 202 a, 202 b may be further connected toland grid array substrates 208 a, 208 b by an array of contacts 206 a,206 b.

The third individual die 202 c may be electrically connected and/orattached to a bottom surface 215 b the second land grid array 208 b by athird array of contacts 206 c on the device side 210 c of the individualdie 202 c. The fourth individual die 202 d may be electrically connectedand/or attached to a top surface 213 c a third land grid array 208 c bya fourth array of contacts 206 d on the device side 210 d of the fourthindividual die 202 d. The third land grid array 208 c may also comprisea bottom surface 215 c. It will be understood by those skilled in theart that the number of levels of die and/or land grid arrays that may bestacked will vary according to a particular design application. Thus,the current embodiment enables the formation of stacked die structuresthat possess a high strength, low stress bond between the stacked die,without the use of an interfacial glue.

FIG. 3 depicts another embodiment of the present invention. FIG. 3illustrates a cross-section of a stacked die structure 316. The stackeddie structure 316 may comprise a first individual die 302 a, a secondindividual die 302 b, a third individual die 302 c, and a fourthindividual die 302 d. The individual die 302 a, 302 b, 302 c, 302 d maycomprise device sides 310 a, 310 b, 310 c, 310 d, respectively, that maypreferably comprise silicon, and non-device sides 312 a, 312 b, 312 c,312 d, respectively, that may preferably comprise a diamond material, orother equivalent films, as are well known in the art. The diamondmaterial may be formed by any such technique known in the art used toform diamond films, such as, but not limited to, plasma enhancedchemical vapor deposition (PECVD).

A first polysilicon layer 311 a, a second polysilicon layer 311 b, athird polysilicon layer 311 c, and a fourth polysilicon layer 311 d, asare well known in the art, may be disposed between the non-device sides312 a, 312 b, 312 c, 312 d and the device sides 310 a, 310 b, 310 c, 310d respectively. The polysilicon layers 311 a, 311 b, 311 c, 311 d mayserve as an adhesion layer between the non-device layers 312 a, 312 b,312 c, 312 d and the device layers 310 a, 310 b, 310 c, 310 b.

The non-device side 312 a of the first individual die 302 a may bebonded to the non-device side 312 b of the second individual die 302 b(by direct silicon to silicon bonding, as described above) to form abond 314 a, similar to the bond 114 in FIG. 1e . The bond 314 a does notcomprise an interfacial glue. In like manner, the non-device side 312 cof the third individual die 302 c may be bonded to the non-device side312 d of the fourth individual die 302 d to form a bond 314 b, that isalso similar to the bond 114 of FIG. 1e , and which does not comprise aninterfacial glue.

The device sides 310 a, 310 b, 310 c, 310 d may comprise an array ofcontacts 306 a, 306 b, 306 c, 306 d such as but not limited to ball gridarray contacts, for example. The array of contacts 306 a may beelectrically connected and/or attached to a bottom surface 315 b of afirst land grid array 308 a. The first land grid array 308 a may alsocomprise a top surface 313 a. The array of contacts 306 b may beelectrically connected and/or attached to a top surface 313 b of asecond land grid array 308 b. The array of contacts 306 c may beelectrically connected and/or attached to a bottom surface 315 b of thesecond land grid array 308 b. The array of contacts 306 d may beelectrically contacted and/or attached to a top surface 313 c of a thirdland grid array 308 c. The third land grid array 308 c may also comprisea bottom surface 315 c. The land grid arrays 308 a, 308 b and 308 c maycomprise an organic land grid array, but may comprise any such suitablesubstrate that may be electrically connected to a semiconductor die.

It will be understood by those skilled in the art that the number oflevels of die that may be stacked will vary according to the particulardesign application. The current embodiment enables the formation ofstacked die structures that possess a high strength, low stress bondbetween the stacked die, without the use of an interfacial glue. Inaddition, since the current embodiment preferably comprises a silicon ondiamond structure, in that the non-device sides 312 a, 312 b, 312 c, 312d preferably comprise diamond and the device sides 310 a, 310 b, 310 c,310 d preferably comprise silicon, the stacked die structure 316 of thecurrent embodiment greatly improves the thermal management capabilitiesof the stacked die structure 316 by enabling heat spreading to occur bythe diamond non-device sides 312 a, 312 b, 312 c, 312 d. As detailedabove, the present invention describes the formation of stacked diestructures that exhibit low stress and high mechanical strength, withoutthe use of interfacial glues between die bonded together.

FIG. 4 is a diagram illustrating an exemplary system capable of beingoperated with methods for fabricating stacked die structures, such asthe stacked die structures 216, 316 of FIGS. 2 and 3 respectively. Itwill be understood that the present embodiment is but one of manypossible systems in which the stacked die structures of the presentinvention may be used. The system 400 may be used, for example, toexecute the processing by various processing tools, such as bondingtools, as are well known in the art, for the methods described herein.

In the system 400, a stacked die structure 403 may be communicativelycoupled to a printed circuit board (PCB) 401 by way of an I/O bus 408.The communicative coupling of the stacked die structure 403 may beestablished by physical means, such as through the use of a packageand/or a socket connection to mount the stacked die structure 403 to thePCB 401 (for example by the use of a chip package and/or a land gridarray socket). The stacked die structure 403 may also be communicativelycoupled to the PCB 401 through various wireless means (for example,without the use of a physical connection to the PCB), as are well knownin the art.

The system 400 may include a computing device 402, such as a processor,and a cache memory 404 communicatively coupled to each other through aprocessor bus 405. The processor bus 405 and the I/O bus 408 may bebridged by a host bridge 406. Communicatively coupled to the I/O bus 408and also to the stacked die structure 403 may be a main memory 412.Examples of the main memory 412 may include, but are not limited to,static random access memory (SRAM) and/or dynamic random access memory(DRAM), and/or some other state preserving medium. The system 400 mayalso include a graphics coprocessor 413, however incorporation of thegraphics coprocessor 413 into the system 400 is not necessary to theoperation of the system 400. Coupled to the I/O bus 408 may also, forexample, be a display device 414, a mass storage device 420, andkeyboard and pointing devices 422.

These elements perform their conventional functions well known in theart. In particular, mass storage 420 may be used to provide long-termstorage for the executable instructions for a method for forming stackeddie structures in accordance with embodiments of the present invention,whereas main memory 412 may be used to store on a shorter term basis theexecutable instructions of a method for forming stacked die structuresin accordance with embodiments of the present invention during executionby computing device 402. In addition, the instructions may be stored, orotherwise associated with machine accessible mediums communicativelycoupled with the system, such as compact disks, read only memories(CD-ROMs), digital versatile disks (DVDs), floppy disks, and carrierwaves, and/or other propagated signals, for example. In one embodiment,main memory 412 may supply the computing device 402 (which may be aprocessor, for example) with the executable instructions for execution.

Although the foregoing description has specified certain steps andmaterials that may be used in the method of the present invention, thoseskilled in the art will appreciate that many modifications andsubstitutions may be made. Accordingly, it is intended that all suchmodifications, alterations, substitutions and additions be considered tofall within the spirit and scope of the invention as defined by theappended claims. In addition, it is appreciated that variousmicroelectronic structures, such as stacked die structures, are wellknown in the art. Therefore, the Figures provided herein illustrate onlyportions of an exemplary microelectronic device that pertains to thepractice of the present invention. Thus the present invention is notlimited to the structures described herein.

What is claimed is:
 1. A structure comprising: a non-device side of afirst die directly bonded to a non-device side of a second die, whereinthe bond between the non-device side of the first die and the non-deviceside of the second die is between silicon surfaces of the non-deviceside of the first die and the non-device side of the second die, whereinthe bond between the non-device side of the first die and the non-deviceside of the second die is by direct silicon to silicon bonding and doesnot comprise a joining material, and wherein the non-device side of thefirst die and the non-device side of the second die are substantially indirect contact with each other.
 2. The structure of claim 1 wherein thenon-device side of the first die and the non-device side of the seconddie comprise silicon.
 3. The structure of claim 1 wherein the non-deviceside of the first die and the non-device side of the second die comprisea diamond film.
 4. The structure of claim 3 wherein a first polysiliconlayer is disposed between the non-device side and the device side of thefirst die, and a second polysilicon layer is disposed between thenon-device side and the device side of the second die.
 5. A structurecomprising: a non-device side of a first die directly bonded to anon-device side of a second die, wherein the bond between the non-deviceside of the first die and the non-device side of the second die isbetween silicon surfaces of the non-device side of the first die and thenon-device side of the second die, wherein the bond between thenon-device side of the first die and the non-device side of the seconddie is by direct silicon to silicon bonding and does not comprise ajoining material, and wherein the non-device side of the first die andthe non-device side of the second die are substantially in directcontact with each other; a first array of contacts disposed on a deviceside of the first die and a second array of contacts disposed on adevice side of the second die; and a first land grid array disposed onthe first array of contacts and a second land grid array disposed on thesecond array of contacts.
 6. The structure of claim 5 wherein thenon-device side of the first die and the non-device side of the seconddie comprise silicon.
 7. The structure of claim 5 wherein the non-deviceportion of the first die and the non-device side of the second diecomprise diamond.
 8. The structure of claim 5 wherein a firstpolysilicon layer is disposed between the device side and the non-deviceside of the first die and a second polysilicon layer is disposed betweenthe device side and the non-device side of the second die.
 9. Thestructure of claim 5 wherein the first land grid array and the secondland grid array comprise a first organic land grid array and a secondorganic land grid array.
 10. The structure of claim 5 wherein the firstarray of contacts and the second array of contacts comprise a first ballgrid array and a second ball grid array.
 11. A microelectronicstructure, comprising: a non-device side of a first die; and anon-device side of a second die directly bonded to the non-device sideof the first die; wherein the bond between the non-device side of thefirst die and the non-device side of the second die is between siliconsurfaces of the non-device side of the first die and the non-device sideof the second die, wherein the bond between the non-device side of thefirst die and the non-device side of the second die is by direct siliconto silicon bonding and does not comprise a joining material, and whereinthe non-device side of the first die and the non-device side of thesecond die are substantially in direct contact with each other, and thenon-device side of the first die and the non-device side of the seconddie comprise a selected one of silicon and a diamond film.
 12. Themicroelectronic structure of claim 11 wherein a first polysilicon layeris disposed between the non-device side and the device side of the firstdie, and a second polysilicon layer is disposed between the non-deviceside and the device side of the second die.
 13. A system comprising: astacked die structure comprising a non-device side of a first diedirectly bonded to a non-device side of a second die, wherein the bondbetween the non-device side of the first die and the non-device side ofthe second die is between silicon surfaces of the non-device side of thefirst die and the non-device side of the second die, wherein the bondbetween the non-device side of the first die and the non-device side ofthe second die is by direct silicon to silicon bonding and does notcomprise a joining material, and wherein the non-device side of thefirst die and the non-device side of the second die are substantially indirect contact with each other; a PCB communicatively coupled to thestacked die structure; and a DRAM communicatively coupled to the stackeddie structure.
 14. The system of claim 13 wherein the stacked diestructure further comprises: a first array of contacts disposed on adevice side of the first die and a second array of contacts disposed ona device side of the second die; and a first land grid array disposed onthe first array of contacts and a second land grid array disposed on thesecond array of contacts.